Industrial

The MM74C373 and MM74C374 are integrated, complementary MOS (CMOS), 8-bit storage elements with 3-STATE outputs. These outputs have been specially designed to drive high capacitive loads, such as one might find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level is applied to the OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74C373 is an 8-bit latch. When LATCH ENABLE is high, the Q outputs will follow the D inputs. When LATCH ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH ENABLE returns high again. The MM74C374 is an 8-bit, D-type, positive-edge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on posi- tive-going transitions of the CLOCK input. Both the MM74C373 and the MM74C374 are being assem- bled in 20-pin dual-in-line packages with 0.300” pin cen- ters. Features I Wide supply voltage range: 3V to 15V I High noise immunity: 0.45 VCC (typ.) I Low power consumption

MM74C32 is a quad 2-input OR gate device from Fairchild Semiconductor Corporation that achieves low power and high noise margin, providing the basic functions used in the implementation of digital integrated circuit systems. It features a wide supply voltage range (3.0V to 15V), guaranteed noise margin (1.0V), high noise immunity (0.45V VCC (typ.)), and low power TTL compatibility (fan out of 2 driving 74L).

This document describes the features and characteristics of the TLF5881 MM54C32 and MM74C32 Quad 2-Input OR Gates. These gates employ complementary MOS (CMOS) transistors to achieve low power and high noise margin. They provide the basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage, resulting in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge damage.

MM54C221-MM74C221 is a dual monostable multivibrator with features such as wide supply voltage range, guaranteed noise margin, and low power consumption.

The MM54C195 is MM74C195 CMOS 4-bit registers features parallel inputs, parallel outputs, J-K serial inputs, shift-load control input and a direct overriding clear. The register has two modes of operation, parallel load and shift. Parallel loading is accomplished by applying the four bits of data and taking the shift-load control of input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting is accomplished synchronously when the shift-load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K, D or T-type flip flop as shown in the truth table.

The MM74C192 and MM74C193 are synchronous 4-bit up/down decade counter and synchronous 4-bit up/down binary counter.

The MM54C192 and MM74C192 are BCD counters, while the MM54C193 and MM74C193 are binary counters. Both counters support counting from 0 to 9 and can be used to perform addition and subtraction operations, respectively. The counters also have carry and borrow outputs, so they can be cascaded using no external circuitry.

This data sheet provides detailed information about the MM74C175 product, including its model, manufacturer, features, package, and pins.

The MM74C174 is a Hex D-Type Flip-Flop produced by Fairchild Semiconductor Corporation. It is constructed with N- and P-channel enhancement transistors, has a wide supply voltage range, high noise immunity, and low power TTL compatibility.

The MM74C154 is a 4-line to 16-line decoder/demultiplexer that is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors.

The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines the particular 1-of-16 inputs which is routed to the output. The data is inverted from input to output. A strobe override places the output of MM74C150 in the logical “1” state and the output of MM82C19 in the high-impedance state. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND.

This document introduces a series of logic gate products, including Quad 2-Input NAND Gate, Quad 2-Input NOR Gate, Hex Inverter, Triple 3-Input NAND Gate, and Dual 4-Input NAND Gate. These products use complementary MOS (CMOS) technology and have wide power supply operating range, low power consumption, high noise immunity, and symmetric controlled rise and fall times. The 54C-74C logic family is functionally and pin compatible with the 54-74 series devices, minimizing design time for designers familiar with the standard 54-74 logic family. All inputs are protected from damage due to static discharge by diode clamps.