The MM54C195 is MM74C195 CMOS 4-bit registers features parallel inputs, parallel outputs, J-K serial inputs, shift-load control input and a direct overriding clear. The register has two modes of operation, parallel load and shift. Parallel loading is accomplished by applying the four bits of data and taking the shift-load control of input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting is accomplished synchronously when the shift-load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K, D or T-type flip flop as shown in the truth table.
The document describes the MM54C195 and MM74C195 CMOS 4-bit registers, which feature parallel inputs and outputs, J-K serial inputs, a shift/load control input, and a direct overriding clear. These devices support two modes of operation: parallel loading and synchronous serial shifting.
| Operating Frequency (Typ.) | 8.5 MHz |
|---|---|
| Supply Voltage Range | 3V to 15V |
The device supports Parallel Load and Serial shifting modes.
Yes, it is described as Tenth power TTL compatible.