Altera Manuals

This document describes the dedicated peripherals that support Altera SoC FPGAs, featuring a microprocessor unit (MPU) with a dual-core ARM Cortex-A9 MPCore processor. Altera's 28-nm Cyclone V and Arria V SoC FPGAs include a rich set of system peripherals.

MAX V Device Handbook

The document provides information about the features and characteristics of the Stratix® III Device Family Pin Connection Guidelines.

This document provides pin connection guidelines for the Cyclone® IV device family. It includes information about the brand, model, features, and characteristics of the products.

This manual is for the Altera HardCopy IV GX and HardCopy IV E series device pin connection guidelines

This document is a technical document released by Altera Corporation about Cyclone® III Device Family Pin Connection Guidelines

This document is a preliminary pin connection guidelines for Altera’s Arria® V Device Family

PCG-01011-1.4 is a pin connection guideline for the Stratix® V E, GS, and GX device families.

Introduces the overview, features, design and applications of the Arria GX device.

This document describes the pin connection guidelines for the Altera Arria II device family

This document describes the contents of the PCN0506 document released by ALTERA Corporation on August 12, 2005. The document describes the change made by ALTERA to add Intel flash memory as a source in the EPC4, EPC8, and EPC16 enhanced configuration devices. This change affects fit and function.

This is an English document, which is the preliminary version of the HardCopy III device family pin connection guidelines released by Altera in 2009.

The document is a handbook for Altera's Stratix II GX device, describing its features and characteristics.