STMicroelectronics manuals, page 56
ST 74LVX257 handbook
The datasheet introduces the characteristics of 74LVX257 low voltage CMOS QUAD 2 CHANNEL MULTIPLEXER (3-STATE), including high speed, 5V input tolerance, power down protection, input voltage range, low power consumption, low noise, symmetrical output impedance, balanced propagation delay, operating voltage range, pin and function compatibility 74 series 257 etc.
ST 74LVX27 handbook
The 74LVX27 is a low voltage CMOS triple 3-input NOR gate fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
ST 74V1G07 handbook
ST 74V1T126 handbook(1)
ST 74V1T14 handbook(1)
ST 74V1G126 handbook(1)
This document describes the features and characteristics of the 74V1G126 single bus buffer, including high-speed transmission, low power dissipation, high noise immunity, etc.
ST 74LVX573 handbook
The 74LVX573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.
ST 74LVX574 handbook
ST 74LVX374 handbook
ST 74LVX373 handbook
The 74LVX373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.
ST 74V1T07 handbook(1)
The 74V1T07 is a high performance CMOS single buffer with high noise immunity and stable output.
ST 74V1G70 handbook(1)
74V1G70 is an integrated circuit
ST 74LVX138 handbook
The 74LVX138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. If the device is enabled, 3 binary select (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient ESD immunity.
ST 74LVX157 handbook
The 74LVX157 is a low voltage CMOS QUAD 2 channel multiplexer fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. It consists of four 2-input digital multiplexers with common select and strobe inputs. When STROBE input is held high, selection of data is inhibited and all the outputs become low. The SELECT decoding determines whether the A or B inputs get routed to their corresponding Y outputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
ST 74LVX174 handbook
74LVX174 is a low voltage CMOS hex D-type flip-flop with clear non inverting fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.