Cypress manuals, page 7
CYPRESS CY62137CV25/30/33 MoBL CY62137CV MoBL handbook
The CY62137CV25/30/33 and CY62137CV are high-performance CMOS static RAMs organized as 128K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular tele- phones.
CYPRESS CY7C68300B/CY7C68301B CY7C68320/CY7C68321 handbook
This document describes the features and characteristics of the EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge products from Cypress Semiconductor Corporation, including fixed-function mass storage device, compliance with USB 2.0 and USB Mass Storage Class standards, support for ATA/ATAPI-6 specification, support for 48-bit addressing, etc.
CYPRESS ISD-300LP Low-Power USB 2.0 to ATA/ATAPI Bridge IC handbook
This document is a user manual for CY7C68310, which mainly introduces the functions, applications, pin definitions, working principles, configuration methods and other information of the product.
CYPRESS SEMICONDUCTOR CY4611B FX2LP USB to ATA/CF Reference Design Notes handbook
This document is the reference design notes for Cypress EZ-USB FX2LP Mass Storage reference design. It introduces the device types, the reference design contents, background information and more.
CYPRESS CY22050 Manual
CY22050 is an integrated phase-locked loop (PLL) general-purpose flash programmable clock generator that can generate six outputs up to 200 MHz. It can generate custom frequencies from an external reference crystal or a driven source. This product is suitable for commercial and industrial applications and offers performance guarantees for an extended temperature range. The flash-programmable technology allows for easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. The parts can be reprogrammed up to 100 times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. The high-performance, low-skew, low-jitter, high-accuracy outputs make it well-suited for commercial, industrial, networking, telecomm, and other general-purpose applications. It operates at 3.3V with a 2.5V output option, making it compatible with standard and low-power systems. The product is packaged in a 16-lead TSSOP, which is an industry standard and saves board space.
CYPRESS CY7C1339F Manual
The product is a 4-Mbit (128K x 32) Pipelined Sync SRAM with registered inputs and outputs for pipelined operation, 128K × 32 common I/O architecture, 3.3V core power supply, 2.5V / 3.3V I/O operation, fast clock-to-output times (250-MHz device for 2.6 ns, 225-MHz device for 2.6 ns, 200-MHz device for 2.8 ns, 166-MHz device for 3.5 ns, 133-MHz device for 4.0 ns, 100-MHz device for 4.5 ns), provides high-performance 3-1-1-1 access rate, user-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences, separate processor and controller address strobes, synchronous self-timed writes, asynchronous output enable, offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages, and “ZZ” Sleep Mode Option.
CYPRESS CY7C130 Data Sheet
This document describes the features and characteristics of the CY7C130/CY7C131 and CY7C140/CY7C141 products produced by Cypress Semiconductor Corporation. These products are 1K x 8 dual-port static RAMs with true dual-ported memory cells that allow simultaneous reads of the same memory location. They are fabricated using 0.65-micron CMOS technology for optimum speed and power. The products offer high-speed access and low operating power. They support fully asynchronous operation, automatic power-down, and port-to-port communication. The CY7C130/CY7C131 can be used as a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device to expand the data bus width. They are suitable for applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.
CYPRESS Ultra37000 CPLD Family handbook
The document describes the Ultra37000™ family of CMOS CPLDs from Cypress Semiconductor Corporation, which provides a range of high-density programmable logic solutions. The product features In-System Reprogrammable™ (ISR™) capability with JTAG interface for reconfigurability, design changes do not cause pinout or timing changes. The features include high density, simple timing model, 3.3V and 5V versions, PCI compatibility, programmable bus-hold capabilities, flexible clocking, consistent package and pinout offering, etc.
CYPRESS CY7C132 Manual
Search for CY7C132-30PC suppliers
CYPRESS SEMICONDUCTOR CY7C68000 Manual
The Cypress EZ-USB TX2™ is a USB 2.0 transceiver, supporting 16-bit 30MHz or 8-bit 60MHz parallel interfaces.
CYPRESS SEMICONDUCTOR CY8C20534 CY8C20434 CY8C20334 CY8C20234 Manual
This document introduces the features and characteristics of PSoC® Mixed-Signal Array, including Low Power CapSense Block, Powerful Harvard Architecture Processor, Flexible On-Chip Memory, Complete Development Tools, Precision, Programmable Clocking and Programmable Pin Configurations.
CYPRESS SEMICONDUCTOR CY7C65640A Manual
TetraHub™ High-Speed USB Hub Controller CY7C65640A is a USB 2.0 hub controller that supports four downstream ports, each with a multi-transaction translator for maximum performance. The controller also supports VID, PID, and DID configuration from external SPI EEPROM and a 24MHz external crystal.
CYPRESS Ultra37000 CPLD Family
The document introduces the Ultra37000 series CMOS CPLDs products from Cypress Semiconductor Corporation. The products feature In-System Reprogrammable™ (ISR™) capability, allowing reconfiguration through JTAG interface. Additionally, the products offer high density, simple timing model, 3.3V and 5V versions, and programmable bus-hold capabilities.
CYPRESS CY7C1327F 4-Mb (256K x 18) Pipelined Sync SRAM Manual
This document is a technical manual for Cypress Semiconductor Corporation's 4-Mb (256K x 18) Pipelined Sync SRAM CY7C1327F, introducing the product's features and characteristics, including registered inputs and outputs, 256K ×18 common I/O architecture, 3.3V / 2.5V I/O operation, fast clock-to-output times, high-performance 3-1-1-1 access rate, user-selectable burst counter, separate processor and controller address strobes, synchronous self-timed writes, asynchronous output enable, JEDEC-standard 100-pin TQFP and 119 Ball BGA packages, and “ZZ” Sleep Mode Option.
CYPRESS CY7C68300B/CY7C68301B CY7C68320/CY7C68321 datasheet
This document describes the features and characteristics of EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge CY7C68300B/CY7C68301B CY7C68320/CY7C68321.