TEXAS Manuals

This document describes the features and characteristics of SN5486, SN54LS86A, SN54S86 SN7486, SN74LS86A, SN74S86, which are quadruple 2-input exclusive-OR gates.

This document describes the SN54LVC06A and SN74LVC06A hex inverter buffers/drivers with open-drain outputs. These devices operate in the voltage range of 1.65V to 3.6V and have fast propagation delay and low power consumption. They can be used as translators in mixed 3.3V/5V system environments.

The eZ430-Chronos™ Development Tool User's Guide is a user guide for the eZ430-Chronos™ development tool, which describes the features and characteristics of the product.

This datasheet introduces the characteristics of four voltage comparators: LM193, LM293, LM393 and LM393A, including operating voltage range, supply current, input bias current, input offset current, input offset voltage, common-mode input voltage range, differential input voltage range, output saturation voltage, etc

This datasheet provides the characteristics of SN54HC573A/SN74HC573A transparent D-type latches. This device has 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

This document describes a 1-bit to 2-bit address driver designed for 2.3V to 3.6V VCC operation. Diodes to VCC have been added on the inputs to clamp overshoot. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The outputs, which are designed to sink up to 12 mA, include series damping resistors to reduce overshoot and undershoot. The ALVCHS162830A is an improved version of the LVCHS162830 (non-A version) and has been optimized for lower power consumption and higher AC drive. Higher AC drive provides capability to drive loads with a faster edge rate. To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

CD54ACT138 and CD74ACT138 are 3-line to 8-line decoders/demultiplexers designed for high-performance memory decoding and data routing applications. They have short propagation delay times and reduced power consumption, and can be used to minimize the effects of system decoding. They incorporate three enable inputs to simplify cascading and/or data reception. They feature balanced propagation delays and SCR-Latchup-resistant CMOS process and circuit design. They support a fanout of up to 15 F devices and exceed 2kV ESD protection.

CD54HC640 and CD74HC640 are inverting buffers. The direction of data flow (A to B, B to A) is controlled by the DIR input. Outputs are enabled by a low on the Output Enable input (OE); a high OE puts these devices in the high impedance state.

The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver from Texas Instruments. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at 3.3V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input. When the G input is high, the outputs switch in phase.

This document is about THS4031 and THS4032, which are ultralow voltage noise, high-speed voltage feedback amplifiers that are ideal for applications requiring low voltage noise, including communications and imaging. The single amplifier THS4031 and the dual amplifier THS4032 offer very good ac performance with 100-MHz bandwidth (G = 2), 100-V/ms slew rate, and 60-ns settling time (0.1%). The THS4031 and THS4032 are unity gain stable with 275-MHz bandwidth. These amplifiers have a high drive capability of 90 mA and draw only a small amount of current.