ANALOG Manuals

ADF7023 is a high performance, low power, ISM band FSK/GFSK/OOK/MSK/GMSK transceiver IC.

This document provides information about the silicon anomalies of the ADF7021 narrow-band transceiver IC and includes workarounds for these issues. One known issue is the inability to access the sync word detect signal on the SWD pin in 4FSK mode.

ADF7020 is a high-performance, ISM band, FSK/ASK transceiver IC. It features low power, low IF, programmable output power, high sensitivity and small package.

This document describes the features and characteristics of the Multichannel ISM Band FSK/GFSK/OOK/GOOK/ASK Transmitter ADF7012 Rev. 0, including single-chip, low power, multichannel operation, programmable output power, and data rates.

The ADF7011 is a low power OOK/ASK/FSK/GFSK UHF transmitter designed for use in ISM band systems. It contains an integrated VCO and Σ-∆ fractional-N PLL. The output power, channel spacing, and output frequency can be programmed with four 24-bit registers.

The ADF7010 is a low power OOK/ASK/FSK/GFSK UHF transmitter designed for use in ISM band systems. It contains an integrated VCO and sigma-delta fractional-N PLL, operating voltage of 2.3V-3.6V, programmable output power of -16dBm to +12dBm, data rate up to 76.8kbps, output current of 28mA, low power consumption, and is used in low cost wireless data transfer, wireless metering, remote control/security systems and keyless entry.

This document describes the features and characteristics of the ADF9010 Rev. 0 analog RF front end for the 900 MHz ISM band.

The AD6624A is part of Analog Devices’ SoftCell® multicarrier transceiver chipset designed for compatibility with Analog Devices’ family of high sample rate IF sampling ADCs (AD6640/ AD6644 12- and 14-bit). The SoftCell receiver comprises a digital receiver capable of digitizing an entire spectrum of carriers and digitally selecting the carrier of interest for tuning and channel selection. This architecture eliminates redundant radios in wireless base station applications. High dynamic range decimation filters offer a wide range of decimation rates. The RAM-based architecture allows easy reconfiguration for multimode applications. The decimating filters remove unwanted signals and noise from the channel of interest. When the channel of interest occupies less bandwidth than the input signal, this rejection of out-of-band noise is called “processing gain.” By using large decimation factors, this “processing gain” can improve the SNR of the ADC by 30 dB or more. In addition, the chipset includes a demodulator, IF filters, and ADC for receiving, demodulating, and digitizing RF signals.

The AD6634 is an 80 MSPS dual-channel WCDMA receive signal processor with wideband inputs and multiple features. It can process two WCDMA channels or four GSM/EDGE, IS136 channels, and has four independent digital receivers. The product also features programmable digital automatic gain control loops, digital resampling, and programmable FIR filters.

AD6635 is a 4-channel, 80 MSPS WCDMA Receive Signal Processor (RSP) that integrates a proprietary ADC, filters, and analog baseband processors to provide a complete WCDMA receiver.

The AD6636 is a 150 MSPS, wideband, digital downconverter (DDC) product from Analog Devices. The product supports 4/6 independent wideband processing channels, and can process 6 wideband carriers (UMTS, CDMA2000). It also features 4 single-ended or 2 LVDS parallel input ports (16 linear bits plus 3-bit exponent), running at 150 MHz. The AD6636 also supports 300 MSPS input using external interface logic, and has three 16-bit parallel output ports, operating up to 200 MHz. The AD6636 supports real or complex input ports, and can perform quadrature correction and dc correction for complex inputs. The product also supports output rates up to 34 MSPS per channel, and can monitor RMS/peak power of input ports. The AD6636 also has programmable attenuator control, for external gain ranging. The product also features 3 programmable coefficient FIR filters per channel, as well as 2 decimating half-band filters per channel. The AD6636 also has 6 programmable digital AGC loops, with a dynamic range of 96 dB. The product also supports synchronous serial I/O operation (SPI®-, SPORT-compatible), and supports 8-bit or 16-bit microport data formats.

This document introduces the features and characteristics of AD6622 four-channel 75 MSPS digital transmit signal processor (TSP).

This document is the datasheet of AD6623, which introduces the functions and features of the chip. The chip is a 4-channel, 104 MSPS digital transmit signal processor (TSP) that supports real or complex output and can be cascaded to increase the number of channels.

This document describes the features and characteristics of Analog Devices' Multichannel Digital Upconverter with VersaCREST™ Crest Reduction Engine AD6633 Rev. Sp0. The product features 4 or 6 wideband digital upconverter channels, and the VersaCREST crest reduction engine reduces demands on external power amplifiers. It also has a 20-bit complex input port (I, Q interleaved), shared among 4 or 6 processing channels. There are two 18-bit output ports for parallel I and Q or a single 18-bit output port for interleaved I and Q. It meets IS-95 requirements with all-pass phase equalizer filters. The product includes programmable RAM coefficient FIR filters (RCF) with resampling FIR interpolating filters, 2 per channel. It also has a fifth-order interpolating CIC filter, 1 per channel. The full complex NCO has 32-bit tuning resolution (fine) with a worst spur better than -105 dBc, 1 per channel. It includes a complex FIR filter for frequency equalization or additional filtering, output automatic gain control, and full complex composite N.