The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop. The 74ALVC162836A is designed with 30 _series resistors in both HIGH or LOW output stages.
The document describes the 74ALVC162836A, an integrated circuit designed as a 20-bit universal bus driver. It features data flow control via output enable (OE), latch enable (LE), and clock inputs (CP). The device includes integrated 30 Ω termination resistors in both HIGH and LOW output stages to minimize noise.
| Supply Voltage Range | 1.2 V to 3.6 V |
|---|---|
| Current Drive | + 12 mA at 3.0 V |
| Output Termination | Integrated 30 Ω resistors |
| Maximum Clock Frequency (Vcc=3.3V) | 240 MHz |
The maximum clock frequency is 240 MHz when the supply voltage is 3.3 V and the load capacitance is 50 pF.
The device operates with a supply voltage range of 1.2 V to 3.6 V.
The current drive capability is +12 mA at 3.0 V.