The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT16823A has two 9-bit wide buffered registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems.
The Philips 74ABT16823A is an 18-bit bus interface register designed to eliminate the need for extra packages when buffering existing registers. It provides two sets of high-speed parallel registers, each 9 bits wide, featuring positive edge-triggered D-type flip-flops with Clock Enable (nCE) and Master Reset (nMR). This component is ideal for parity bus interfacing in high microprogrammed systems where high speed, light loading, or increased fan-in are required.
| Number of registers | Two sets of high speed parallel registers |
|---|---|
| Data width per register | 9-bit wide |
| Output capability (sourcing) | +64 mA |
| Output capability (sinking) | -32 mA |
| Latch-up protection | > 500 mA |
| ESD protection (MIL STD) | > 2000 V |
| Operating temperature range | -40 °C to +85 °C |
It is designed to eliminate extra packages required to buffer existing registers and provide extra data width for wider data/address paths.
Yes, live insertion/extraction is permitted for this component.