This is a user manual for ZiLOG Z80 CPU, which introduces the functions and features of Z80 CPU
This manual describes the Z80 8‑bit CPU architecture, its registers, ALU functions, instruction formats, and pin definitions. It includes timing diagrams, interrupt handling procedures, and examples of hardware and software implementation.
The document also contains extensive instruction set tables, assembly language details, status flag descriptions, and guidance for interfacing dynamic memory and peripheral devices.
| Typical clock speed | 4 MHz |
|---|
OUTD transfers a byte from the memory location pointed to by HL to an I/O port selected by register C, then decrements B and HL.
At 4 MHz, OTDR requires 5.25 T‑states per execution when B ≠ 0, and 4 T‑states when B = 0.