This datasheet describes the WIZnet W5500, a full hardware TCP/IP embedded Ethernet controller integrating protocol stacks and PHY for 10/100Mbps connections.
The document details the WIZnet W5500, an embedded Ethernet controller that integrates a full hardware TCP/IP stack with MAC and PHY layers. It supports protocols including TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE, allowing users to implement network applications using simple socket programming.
The datasheet provides comprehensive information on the device's features, such as support for 8 independent hardware sockets, a high-speed SPI interface up to 80MHz, power-saving modes (Wake-on-LAN), and an internal 32KB buffer. It includes detailed pin descriptions, register definitions, electrical specifications, and application guidelines. This manual is written in Chinese.
| Supported Protocols | TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE |
|---|---|
| Internal Buffer Size | 32KB |
| Number of Sockets | 8 |
| SPI Interface Speed | Up to 80MHz |
| Operating Voltage | 3.3V |
| Package Type | LQFP48 Lead-free |
The theoretical maximum SPI clock frequency is 80MHz.
No, it does not support automatic MDIX; users must use straight-through or crossover cables manually.
A 12.4KΩ resistor with 1% accuracy is required for the EXRES1 pin.