The WIZnet W5500 is a full‑hardware TCP/IP Ethernet controller with integrated MAC/PHY, 8 sockets and a high‑speed SPI interface.
The W5500 Ethernet controller integrates a complete TCP/IP stack, supporting protocols such as TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE. It provides eight independent hardware sockets, a 32 KB on‑chip buffer, and operates at 3.3 V with 5 V‑tolerant I/O. The device connects to a host MCU via an SPI interface that can run up to 80 MHz.
This datasheet details the pin assignment, host interface specifications, register map, memory organization, electrical characteristics, and package dimensions of the W5500. It also includes information on power consumption, clock requirements, and mechanical drawing of the LQFP48 package. This manual is written in Chinese.
| Hardware sockets | 8 sockets |
|---|---|
| On‑chip buffer memory | 32 KB |
| Ethernet speed | 10/100 Mbps |
| Operating voltage | 3.3 V core, 5 V I/O tolerant |
| Package | LQFP48 7 mm × 7 mm, 0.5 mm pitch |
The W5500 supports eight independent hardware sockets.
No, the W5500 does not support automatic polarity reversal; a straight‑through cable must be used for connections to switches or routers.
The device includes a 32 KB on‑chip buffer for Ethernet packet handling.