The WIZnet W5500 datasheet provides detailed specifications, pin assignments, registers, and electrical characteristics of the full‑hardware TCP/IP Ethernet…
The W5500 is a full‑hardware TCP/IP embedded Ethernet controller that integrates a MAC, PHY, and a complete TCP/IP stack, enabling simple network connectivity for embedded systems. It supports up to eight independent hardware sockets and offers a high‑speed SPI interface.
Key features include an internal 32 KB buffer, support for TCP, UDP, ICMP, IPv4, ARP, IGMP and PPPoE, power‑down and Wake‑on‑LAN modes, and a 3.3 V core with 5 V‑tolerant I/O. The datasheet covers pin assignments, host interface details, register maps, electrical specifications, and package information. This manual is written in Chinese.
| Number of hardware sockets | 8 |
|---|---|
| SPI clock rate | Up to 80 MHz |
| Operating voltage | 3.3 V core, I/O 5 V tolerant |
| Internal buffer size | 32 KB |
| Supported protocols | TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE |
| Package | LQFP48, 7 × 7 mm, 0.5 mm pitch |
It supports eight independent hardware sockets for simultaneous communication.
The SPI interface can operate at up to 80 MHz.
The device runs on a 3.3 V core voltage and its I/O pins are tolerant up to 5 V.
Yes, it provides a network wake‑up (WOL) mode.