The Gowin GW1NSER series secure FPGA datasheet provides features, architecture, electrical characteristics, and ordering information.
The GW1NSER series is a secure FPGA family from Gowin, offering a Cortex‑M3 core, configurable logic blocks, and a variety of I/O standards including LVDS and DDR. The device integrates on‑chip memory such as BSRAM, flash, and optional HyperRAM or NOR Flash, and supports multiple programming modes.
The datasheet details the device architecture, I/O bank distribution, electrical specifications, and packaging options. It also lists ordering information, speed‑grade designations, and the supported configuration interfaces for system designers. This manual is written in Chinese.
| Core supply voltage | 1.2 V |
|---|---|
| Maximum VCC current | 100 mA |
| Maximum VSS current | -100 mA |
| Leakage current (IINJ) | ±5 mA |
| AHB clock frequency (fHCLK) | 0‑80 MHz |
| APB clock frequency (fPCLK) | 0‑80 MHz |
It supports up to six modes, including self‑boot, dual‑boot, MSPI, SSPI, CPU, and SERIAL.
The core supply voltage is 1.2 V.
The AHB clock can run up to 80 MHz.