User manual for the Alinx AXU 5EV-E FPGA development board, covering hardware overview, memory, interfaces and connector pin‑assignments.
The Alinx AXU 5EV-E board is a compact FPGA development platform built around a Xilinx Zynq UltraScale+ MPSoC (XCZU5EV‑2SFVC784I). It integrates a 4 GB DDR4 memory subsystem on the processing system side, a 1 GB DDR4 on the programmable logic side, 256 Mbit QSPI flash, 8 GB eMMC flash and a variety of high‑speed interfaces such as USB 3.0, PCIe Gen2, Gigabit Ethernet and HDMI.
The board measures only 3.15 × 2.36 inches and provides four board‑to‑board connectors that expose PS MIO, MGT transceivers, USB, Ethernet, SD, and many GPIOs. Power is split into four domains (Full, Low, PL, Battery) and the design includes on‑board temperature and voltage monitoring.
| FPGA Chip | Xilinx Zynq UltraScale+ MPSoC XCZU5EV‑2SFVC784I |
|---|---|
| PS DDR4 Memory Capacity | 4 GB (4 × 1 GB chips, 64‑bit bus) |
| PL DDR4 Memory Capacity | 1 GB (1 × 1 GB chip, 16‑bit bus) |
| Maximum DDR4 Speed (PS side) | 1200 MHz (data rate 2400 Mbps) |
| Maximum DDR4 Speed (PL side) | 1066 MHz (data rate 2132 Mbps) |
| QSPI Flash | 256 Mbit |
| eMMC Flash | 8 GB |
| Board Dimensions | 3.15 × 2.36 inches |
| Power Supply Domains | Four‑part division: Full, Low, PL, Battery |
The PS side has four 1 GB DDR4 chips, providing a total of 4 GB of memory.
The design supports a four‑part power division: Full, Low, PL and Battery domains.