Vishay Sfernice P Thin Film, PRA Array, CHP Thick Film Application Note

About this manual

This application note explains how power dissipation in Vishay Sfernice high‑precision thin‑film, PRA array and CHP thick‑film chip resistors is managed through thermal modeling. It covers heat flow paths, thermal resistance values (Rth jsp, Rth spa) and the impact of PCB design on component temperature.

The document provides experimental data for various PCB configurations (mCu, sCu, MCu) and presents derating equations and curves that allow designers to calculate the maximum allowable power for a given ambient temperature and thermal resistance. Practical guidance for using enlarged terminals and achieving higher power densities is also included. This manual is written in Chinese.

What's inside

• Abstract
• Thermal Model
• Data
• Derating Method
• Amplified Terminals
• Conclusion
• PCB Configurations

Specifications

Frequently asked questions

What is the maximum allowable junction temperature for Vishay Sfernice chip resistors?

The maximum junction temperature is 155 °C.