This document is a user guide for Altera POS-PHY Level 4 MegaCore Function
The POS-PHY Level 4 MegaCore Function performs high-speed cell and packet transfers between physical and link-layer devices, compliant with the Optical Internetworking Forum (OIF) System Packet Interface Level 4 (SPI-4.2) standard. It supports various Altera device families, including Stratix III, IV, V, and Cyclone series, with data rates up to 1,250 Mbps depending on the specific family.
The document details the design flow, parameter settings, and functional descriptions for both receiver and transmitter features. It includes information on block descriptions, error handling, clock structures, and provides testbench examples and board design pin constraints for implementation.
| Compliance Standard | OIF-SPI4-02.1, October 2003 |
|---|---|
| Max Data Rate (Stratix III/IV/V) | 1,250 Mbps |
| Max Data Rate (Stratix II) | 1,040 Mbps |
| Max Data Rate (Stratix GX) | 1,000 Mbps |
| Max Data Rate (Stratix) | 840 Mbps |
| Max Data Rate (Cyclone III/II/Cyclone) | 622 Mbps (64 bit data path) |
| Max Data Rate (Cyclone III/II/Cyclone 32-bit) | 250 Mbps |
| Max Ports | 256 |
| Data Path Widths | 128 bits, 64 bits, 32 bits |
It is compliant with the Optical Internetworking Forum (OIF) System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1 standard.
Supported families include Arria GX, Cyclone, Cyclone II, Cyclone III, Cyclone IV, HardCopy II/III/IV E, and Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix V.