This is a production data sheet on a 32-bit Power Architecture® based MCU for automotive powertrain applications.
This document is a datasheet for the SPC563M64L5 and SPC563M64L7 microcontrollers, which are 32-bit Power Architecture Book E compliant e2002335 CPU core complex devices. These chips are specifically designed for automotive powertrain applications and feature a single-issue architecture with variable length encoding (VLE) enhancements for code size reduction. Key components include a 32-channel DMA controller, an interrupt controller handling 364 selectable-priority sources, and an FMPLL.
| CPU Core | 32-bit Power Architecture Book E compliant e2002335 |
|---|---|
| Flash Memory | Up to 1.5 Mbyte |
| Static RAM | Up to 94 Kbyte |
| DMA Channels | 32-channel |
| Interrupt Sources | 364 selectable-priority |
| eTPU Channels | 32 standard |
| eMIOS Channels | 16-channels |
| Package Types | LQFP100, LQFP144, LQFP176, LBGA208 |
The Fetch Accelerator allows for single cycle Flash access at 80 MHz.
The Interrupt controller handles 364 selectable-priority interrupt sources.