32-bit MCU family built on the Power Architecture® for automotive body electronics applications
This document describes the SPC560B54x/SPC560B60x/SPC560B64x family of 32-bit system-on-chip (SoC) microcontrollers built on Power Architecture technology. Designed for automotive body electronics applications, these devices feature a high-performance 64 MHz e200z0h CPU, extensive memory options with ECC, and various communication interfaces including FlexCAN, LINFlex, and DSPI.
The datasheet provides comprehensive technical specifications covering electrical characteristics, thermal data, package mechanical drawings, and ordering information. It details the device's low-power capabilities, debugging features via Nexus interfaces, and specific configurations for different package types such as LQFP and LBGA.
| CPU Core | 64 MHz e200z0h |
|---|---|
| Architecture | 32-bit Power Architecture |
| Code Flash Memory | Up to 1.5 MB |
| Data Flash Memory | 64 KB |
| SRAM | Up to 96 KB |
| External Interrupts | Up to 51 lines |
| ADC Channels | Up to 81 channels |
| Operating Temperature | -40 to 125 °C |
| Packages | LQFP100, LQFP144, LQFP176, LBGA208 |
The CPU operates at speeds of up to 64 MHz.
The maximum on-chip Code Flash size is 1.5 MB.
The available packages are LQFP100, LQFP144, LQFP176, and LBGA208.