This application note explains the mechanism of the interrupt management hardware in the STR91x microcontroller family, and also provides application developers with software recommendations for interrupt handling.
The document details the Vectored Interrupt Controller (VIC) architecture within the STR91x microcontroller, which is implemented by daisy-chaining two standard ARM PrimeCell VICs to support 32 interrupt lines. It covers both Fast Interrupt Request (FIQ) and IRQ configurations, explaining priority levels, vectored handling mechanisms, and simple non-vectored handling methods.
The FIQ service routine must be implemented at address 0x1C.
When an IRQ interrupt occurs, the CPU jumps to address 0x18.