ANALOG DEVICES ADuC845/ADuC847/ADuc848: Anomaly Sheet (Rev A 2004-05-01-)

About this manual

This anomaly sheet details specific bugs and limitations found in Silicon Revision B of the ADuC845, ADuC847, and ADuC848 Multichannel 24-/16-Bit ADCs with Embedded Flash and Single-Cycle MCU. The document covers seven distinct issues affecting interrupts, PWM operation, I2C bus access, ADC noise performance, watchdog timer behavior, stack pointer initialization in ULOAD mode, and level-triggered interrupt timing.

What's inside

• Interrupts During Reading/Writing to DATAFLASH/EE
• PWM Operation
• I2C Operation
• ADC Noise
• Watchdog Timer
• Stack Pointer in ULOAD Mode
• Level-Triggered Interrupt Operation

Frequently asked questions

What is the workaround for interrupts occurring during DATAFLASH/EE read or write operations?

Disable all interrupts prior to a read or write operation by setting the EA bit to 0.

How should ADC noise performance issues at maximum clock frequency be handled?

Set the CD bits in the PLLCON SFR to 3 or greater for the duration of an ADC conversion.

What is the required workaround if a Watchdog Timer interrupt sets up a reset that gets ignored?

Execute a double write to WDCON inside the ISR: first reset the timer, then set the timeout.

How should the stack pointer be initialized in ULOAD mode to avoid conflicts?

Manually change the stack pointer address to 07H or the required entry address using MOV SP, #07H.