This file describes how to configure the programmable PLL on the ADSP-2191
The document provides an overview of the ADSP-2191's internal clock multiplier, which allows for flexible clock modes beyond the fixed 2x input rate found in previous families. It details how to configure the PLL to run faster than the input clock or enter a bypass mode to reduce power usage.
The text explains the function of specific pins (MSELx, DF, BYPASS) and their role during reset initialization. It outlines system considerations for these pins when used as general-purpose flags or connected to external SPI devices, offering scenarios with pull-up/pull-down resistors or multiplexing circuits to ensure valid timing ratios.
The PLL supports a user-programmable multiplication of the input clock ranging from 1 to 32, including some fractional values.
The MSELx and DF pins must be in a valid configuration ratio for a period not exceeding 15 CLKIN cycles following the assertion of /Reset.
When the DF pin is set to 1, the input clock is divided by two to ensure the HCLK never exceeds 100Mhz.