This document is about ADSP-2196 ADSP-219x DSP CORE FEATURES, including instruction cycle time, code compatibility, storage space, address generation and other characteristics.
This document provides preliminary technical data for the Analog Devices ADSP-2196 DSP microcontroller. It outlines the device's core features, including a 6.25 ns instruction cycle time and compatibility with the ADSP-218x family, alongside a functional block diagram. The datasheet details the architecture of the DSP core and peripherals, covering memory spaces, interrupt handling, DMA controllers, and various serial ports such as SPI and UART.
| Instruction Cycle Time | 6.25 ns |
|---|---|
| Sustained Performance | 160 MIPS |
| On-Chip RAM | 16K Words |
| On-Chip ROM | 16K Words |
| Operating Voltage | 2.5 V |
The device supports up to 160 MIPS sustained performance.
The internal instruction cycle time is 6.25 ns.
The chip includes 16K words of on-chip RAM.
Up to 11 DMA channels can be active at any given time.