This document describes the features and performance of Analog Devices' ADSP-2185 DSP microcomputer. It has a 30 ns instruction cycle time and 33 MIPS sustained performance, with support for single-cycle instruction execution and single-cycle context switch. The product features a 3-bus architecture that allows dual operand fetches in every instruction cycle. It also includes a power-down mode with low CMOS standby power dissipation and 100 cycle recovery from power-down condition, as well as low power dissipation in idle mode. The ADSP-2185 is code compatible with the ADSP-2100 family and includes instruction set extensions. It has 80K bytes of on-chip RAM, configured as 16K words of on-chip program memory RAM and 16K words of on-chip data memory RAM. The product has independent ALU, multiplier/accumulator, and barrel shifter computational units, along with two independent data address generators and a powerful program sequencer. It also features a programmable 16-bit interval timer with prescaler.
The ADSP-2185 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high-speed numeric processing applications. It combines the ADSP-2100 family base architecture with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, and extensive interrupt capabilities. The device integrates 80K bytes of on-chip memory configured as 16K words of program RAM and 16K words of data RAM.
| Instruction Cycle Time | 30 ns |
|---|---|
| Sustained Performance | 33 MIPS |
| On-Chip Program Memory | 16K Words |
| On-Chip Data Memory | 16K Words |
| Package Type | 100-Lead TQFP |
The ADSP-2185 operates with a 30 ns instruction cycle time.
The ADSP-2185 integrates 80K bytes of on-chip memory configured as 16K words of program RAM.
The EZ-ICE emulator supports up to 20 breakpoints.