This document describes the features and performance of Analog Devices' ADSP-2185 DSP microcomputer. It has a 30 ns instruction cycle time and 33 MIPS sustained performance, with support for single-cycle instruction execution and single-cycle context switch. The product features a 3-bus architecture that allows dual operand fetches in every instruction cycle. It also includes a power-down mode with low CMOS standby power dissipation and 100 cycle recovery from power-down condition, as well as low power dissipation in idle mode. The ADSP-2185 is code compatible with the ADSP-2100 family and includes instruction set extensions. It has 80K bytes of on-chip RAM, configured as 16K words of on-chip program memory RAM and 16K words of on-chip data memory RAM. The product has independent ALU, multiplier/accumulator, and barrel shifter computational units, along with two independent data address generators and a powerful program sequencer. It also features a programmable 16-bit interval timer with prescaler.