The document describes the features and characteristics of the SHARC (Super Harvard Architecture Computer) Family DSP Microcomputer, which is suitable for communications, graphics, and imaging applications. The product features a high-performance signal processor, four independent buses, 32-bit IEEE floating-point computation units, dual-ported on-chip SRAM, and integrated I/O peripherals, among others.
The document is a technical datasheet for the ADSP-21061 and ADSP-21061L processors from Analog Devices. These devices are part of the SHARC (Super Harvard Architecture) family and function as high-performance signal processing microcomputers optimized for communications, graphics, and imaging applications.
The datasheet details the processor's architecture, including a 32-bit IEEE floating-point core with dual data address generators and integrated multiprocessing features. It provides comprehensive information on electrical characteristics, timing specifications, package options (such as MQFP and PBGA), and interfacing capabilities for off-chip memory and host processors.
| Instruction Cycle Time | 20 ns |
|---|---|
| Peak Performance | 120 MFLOPS |
| On-Chip SRAM Size | 1M bit |
| Off-Chip Memory Addressable Range | 4 gigawords |
| DMA Channels | 6 |
| Serial Ports Speed | 40 Mbps |
The processor achieves a peak performance of 120 MFLOPS.
Yes, it is code and function-compatible with the ADSP-21020, ADSP-21060, and ADSP-21062.
Available packages include a 240-lead MQFP, thermally enhanced MQFP, and a 225-ball plastic ball grid array (PBGA).