This data sheet introduces the AD9559 device, a dual PLL, quad input, multiservice line card adaptive clock translator. It supports GR-1244 layer 3 stability and has smooth reference switching with virtually no disturbance to output phase in holdover mode. It also supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems.
The AD9559 is a low loop bandwidth clock multiplier designed to provide jitter cleanup and synchronization for systems such as synchronous optical networks (SONET/SDH). It generates an output clock synchronized to up to four external input references and features a digital PLL to reduce input time jitter or phase noise. The device operates over an industrial temperature range of −40°C to +85°C and includes adaptive clocking for dynamic adjustment of feedback dividers.
Key features include support for GR-1244 Stratum 3 stability in holdover mode, smooth reference switchover, and Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems. The chip includes dual digital PLL architecture with four reference inputs, programmable dividers, and a 72-lead LFCSP package.
| Operating Temperature Range | -40°C to +85°C |
|---|---|
| Package Type | 72-lead LFCSP |
| Supply Voltage VDD3 | 3.135 V to 3.465 V |
| Supply Voltage VDD | 1.71 V to 1.89 V |
| Reference Input Frequencies | 2 kHz to 1250 MHz |
| Output Frequencies | 262 kHz to 1250 MHz |
The AD9559 operates over an industrial temperature range of −40°C to +85°C.
The VDD3 supply voltage ranges from 3.135 V to 3.465 V.
The maximum typical supply current (IVDD) for all blocks running is 320 mA.