This document introduces how Blackfin® family processors can be integrated with a mixed-signal front-end (MxFE) for a variety of real-time applications.
This document details a real-time solution for wireless infrastructure using the Blackfin processor family integrated with the AD9866 Mixed-Signal Front-End (MxFE) device. The architecture connects the 12-bit data converters of the MxFE directly to the Blackfin's parallel peripheral interface (PPI) without external logic, utilizing a half-duplex communication scheme. The system operates with a maximum system clock frequency of 133 MHz and a data clock up to 60 MHz, achieving a bidirectional throughput of over 50 megabytes/second.
| Data Converters | 12-bit |
|---|---|
| Data Clock Frequency | up to 60 MHz |
| Maximum Throughput | over 50 megabytes/second |
The ADSP-BF53 1/BF532/BF533 line of processors are suitable as they have a single PPI.
Data transfer direction is managed in software using a block of configuration code placed in an interrupt service routine (ISR).