This document describes how to configure the ADV7401/ADV7403 CP core to process non-standard video formats. It includes information on how to select the appropriate PRIM_MODE[3:0]/VID_STD[3:0], program the latch clock, PLL_DIV_RATIO[11:0] and FR_LL[10:0].
This document describes how to configure the Component Processor (CP) core within the ADV7401/ADV7403 integrated circuits to process high-definition, progressive scan, and graphics standards not covered by the default PRIM_MODE and VID_STD controls. Examples include nonstandard SMPTE HD standards like 720p/50 Hz and 1080i/50 Hz, as well as RGB graphics formats such as MAC 13 and MAC 16.
The guide details a four-step configuration process: selecting the appropriate PRIM_MODE and VID_STD settings, programming the latch clock, configuring the PLL divider ratio for pixel clock generation, and setting the free-run line length. It includes worked examples for specific formats like 720p at 50 Hz and MAC 16, providing specific register values and calculation methods.
The component processor can be programmed to support SMPTE HD standards like 720p/50 Hz and 1080i/50 Hz, as well as RGB nonstandard graphics formats such as MAC 13 and MAC 16.
The maximum sample rate of the ADC is 140 MHz, which limits the supported pixel clock frequency to this value.
The device can process higher resolution formats by using the PLL to generate a lower pixel clock, which reduces the horizontal resolution to fit within the ADC's sample rate.