Unitrode UCC1921/UCC2921/UCC3921 Latchable Negative Floating Hot Swap Power Manager Datasheet

This file introduces the features and characteristics of the UCC3921 series negative floating hot swap power managers, including precision fault threshold, programmable average power limiting, linear current control, overcurrent limit and fault time, fault output indication signal, automatic retry mode or latched operation mode, shutdown control, undervoltage lockout, 250µs glitch filter on the SDFLTCH pin, etc.


Unitrode UCC1921/UCC2921/UCC3921 Latchable Negative Floating Hot Swap Power Manager Datasheet - cover page
Brand
UNITRODE
Document type
Datasheet
Language
English
Pages
11
File format
PDF
File size
437 KB
Published
01 August, 2012
Updated
30 September, 2023
MD5 checksum
1678B7A528A46871DEFF3A9B9A50AC4F

About this manual

The UCC1921, UCC2921, and UCC3921 family provides complete power management, hot swap, and fault handling capability. The IC is referenced to the negative input voltage and is powered through an external resistor connected to ground, which is essentially a current drive as opposed to the traditional voltage drive.

Key features include precision fault threshold programming for average power limiting, linear current control, overcurrent limit, and fault time. It offers automatic retry mode or latched operation modes with a 250µs glitch filter on the SDFLTCH pin. The device includes undervoltage lockout and is available in 8-pin DIL and SOIC packages.

What's inside

  • Features Description
  • Absolute Maximum Ratings
  • Electrical Characteristics
  • Pin Descriptions
  • Application Information

Frequently asked questions

What is the maximum allowable sourcing current limit for the UCC3921?

The maximum allowable sourcing current is programmed using a voltage divider from VDD to generate a fixed voltage on the IMAX pin.

How is the fault time for the UCC3921 determined?

A capacitor must be connected to the CT pin to set the fault time, which must be longer than the time to charge the external load capacitance.

What is the minimum duration required to toggle the SDFLTCH pin to reset a latched device?

To reset the latched off device, the SDFLTCH pin must be toggled high for a duration greater than 1ms.

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