National Semiconductor ADC081000 Datasheet

The ADC08100 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 20 MSPS to 100 MSPS with outstanding dynamic performance over its full operating range while consuming just 1.3 mW per MHz of clock frequency. That’s just 130 mW of power at 100 MSPS. Raising the PD pin puts the ADC08100 into a Power Down mode where it consumes just 1 mW. The unique architecture achieves 7.4 Effective Bits with 41 MHz input frequency. The excellent DC and AC characteristics of this device, together with its low power consumption and single +3V supply operation, make it ideally suited for many imaging and communications applications, including use in portable equipment. Furthermore, the ADC08100 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08100’s reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 3V or 2.5V logic. The digital inputs (CLK and PD) are TTL/CMOS compatible. The ADC08100 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of −40˚C to +85˚C.


National Semiconductor ADC081000 Datasheet - cover page
Brand
National Semiconductor
Category
AD CONVERTER
Document type
Datasheet
Language
English
Pages
3
File format
PDF
File size
110 KB
Published
04 July, 2012
Updated
29 September, 2023
MD5 checksum
3C23C7A0E6AC02E57E238528C6ED5916

About this manual

The ADC081000 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.6 GSPS while consuming a typical 1.4 Watts from a single 1.9 Volt supply at 1.0 GSPS.

The device features a unique folding/interpolating architecture and fully differential comparator design, enabling a very flat SINAD response beyond Nyquist with a high ENOB of 7.5 bits at a 100 MHz input signal. It includes an internal sample-and-hold amplifier and outputs offset binary coding via LVDS digital outputs compliant with IEEE 1596.3-1996.

What's inside

  • General Description
  • Features
  • Applications
  • Block Diagram
  • Ordering Information
  • Pin Configuration
  • Physical Dimensions

Specifications

Resolution8 Bits
Max Conversion Rate1 GSPS (min)
ENOB @ 100 MHz Input7.5 Bits (typ)
DNL+0.25 LSB (typ)
Conversion Latency7/8 Clock Cycles
PSRR40 dB (typ)
Operating Power Consumption1.4 W (typ)
Power Down Mode Consumption5 mW (typ)
Operating Temperature Range-40°C < T, < +85°C

Frequently asked questions

What is the maximum sampling rate of the ADC081000?

The device can sample signals at rates up to 1.6 GSPS.

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