The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers. The CS18LV20483 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages.
The CS18LV20483 is a high-performance, high-speed, and super low-power CMOS Static Random Access Memory organized as 262,144 words by 8 bits. It operates from a wide range of 2.7 to 3.6V supply voltage with advanced circuit techniques providing high speed and low power features.
| Organization | 262,144 words by 8 bits |
|---|---|
| Typical Standby Current (CMOS) | 0.50 uA |
| Maximum Access Time @ 3.0V | 55/70ns |
| Operating Temperature (Commercial) | 0 to +70°C |
| Operating Temperature (Industrial) | -40 to +85°C |
The maximum operating current is 2mA at 1MHz.
Yes, the device has an automatic power down feature when the chip is deselected.
It is available in JEDEC standard 32-pin TSOP (8x13.4 mm), TSOP (8x20mm), TSOP (Il) (400mil) and SOP (450 mil).