CHIPLUS CS18LV02565 SRAM Datasheet

CS18LV02565 is a high performance, high speed and super low power CMOS static random access memory organized as 32,768 words by 8 bits. It operates on a single 4.5 to 5.5V supply voltage. The memory features advanced CMOS technology and circuit techniques, providing high speed, super low power consumption, and a maximum access time of 55/70ns in 5.0V operation. It supports easy memory expansion with /CE and /OE options. The memory also has an automatic power down feature that significantly reduces power consumption when the chip is deselected. It is available in JEDEC standard 28-pin TSOP I (8x13.4 mm), SOP (330 mil), and PDIP (600 mil) packages.


CHIPLUS CS18LV02565 SRAM Datasheet - cover page
Brand
CHiPLUS
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
14
File format
PDF
File size
294 KB
Published
09 May, 2012
Updated
28 September, 2023
MD5 checksum
01751599FCCCDF21263245EB30F4E7E4

About this manual

The CS18LV02565 SRAM from CHIPLUS provides 32 K words of 8‑bit storage, operating from a single 4.5 V to 5.5 V supply. It features a maximum access time of 55 ns (typical) to 70 ns at 5 V, ultra‑low standby current of about 1 µA, and optional power‑down mode when deselected.

The device is offered in JEDEC‑standard 28‑pin TSOP, SOP and PDIP packages and supports a wide temperature range (commercial 0 °C to 70 °C, industrial –40 °C to 85 °C). Electrical characteristics include input capacitance of 6 pF, output capacitance of 8 pF, and a power dissipation rating of 1 W.

What's inside

  • General Description
  • Features
  • Product Family
  • Pin Configurations
  • Pin Descriptions
  • Absolute Maximum Ratings
  • Operating Range
  • Electrical Characteristics
  • Data Retention Characteristics
  • Package Dimensions
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