The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers. The CS18LV20483 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages.
The CS18LV20483 is a high‑performance static random‑access memory organized as 262,144 words × 8 bits. It operates over a wide supply range of 2.7 V to 3.6 V and features ultra‑low standby current and fast access times, making it suitable for power‑sensitive applications.
Key features include active‑low chip‑enable and output‑enable inputs, three‑state TTL‑compatible outputs, automatic power‑down when deselected, and data‑retention capability down to 1.5 V. The device is offered in several JEDEC‑standard 32‑pin packages such as sTSOP, TSOP, TSOP (II) and SOP.
| Supply Voltage Range | 2.7 V – 3.6 V |
|---|---|
| Typical Standby Current | 0.50 µA |
| Maximum Access Time | 55 ns (typ) / 70 ns (max) at 3.0 V |
| Available Packages | 32‑pin sTSOP, TSOP, TSOP (II), SOP |
| Data Retention Supply Voltage | 1.5 V |
| Industrial Operating Temperature | -40 °C to 85 °C |
It operates from 2.7 V up to 3.6 V.
The typical standby (CMOS) current is 0.50 µA.
It is available in 32‑pin sTSOP, TSOP, TSOP (II) and SOP packages.
The maximum read access time is 55 ns to 70 ns at a 3.0 V supply.