CHiPLUS Manuals

The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers. The CS18LV20483 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages.

CS18LV02565 is a high performance, high speed and super low power CMOS static random access memory organized as 32,768 words by 8 bits. It operates on a single 4.5 to 5.5V supply voltage. The memory features advanced CMOS technology and circuit techniques, providing high speed, super low power consumption, and a maximum access time of 55/70ns in 5.0V operation. It supports easy memory expansion with /CE and /OE options. The memory also has an automatic power down feature that significantly reduces power consumption when the chip is deselected. It is available in JEDEC standard 28-pin TSOP I (8x13.4 mm), SOP (330 mil), and PDIP (600 mil) packages.

The CS18LV10245 is a high performance, high speed and super low power CMOS Static Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of 4.5 to 5.5V supply voltage.

The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers. The CS18LV20483 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages.