CY7C441 and CY7C443 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. The CY7C441 has a 512 word by 9 bit memory array, while the CY7C443 has a 2048 word by 9 bit memory array. These devices provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. Both FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW). When ENW is asserted, data is written into the FIFO.
The CY7C441 and CY7C443 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. Both devices are fabricated using 0.65 micron CMOS technology and feature TTL compatibility, parity generation/checking, and independent read/write enable pins.
| Memory Array Size (CY7C441) | 512 words x 9 bits |
|---|---|
| Memory Array Size (CY7C443) | 2,048 words x 9 bits |
| Maximum Frequency | 83.3 MHz |
| Operating Current (Commercial) | 70 mA |
| Package Type | 32-Pin PLCC |
Yes, the read (CKR) and write (CKW) clocks may be tied together for single-clock operation or run independently.
The CY7C441 has a 9-bit wide memory array with 512 words.
Clock frequencies up to 83.3 MHz are acceptable for operation.