The SM5824N is a variable‑length static shift register LSI designed for high‑speed digital signal‑processing applications. It provides a 10‑bit wide register, selectable shift lengths from 2 to 65 steps, and TTL‑compatible inputs and outputs with tristate capability.
The device operates from a 4.75 V to 5.25 V supply, supports a maximum clock frequency of 33.3 MHz, and is supplied in a 30‑pin shrink DIP package. Detailed pin descriptions, electrical characteristics, and timing parameters are provided for system integration.
| Supply voltage range | 4.75 V to 5.25 V |
|---|---|
| Maximum clock frequency | 33.3 MHz |
| Register width | 10‑bit |
| Shift‑register steps | 2 to 65 steps |
| Package type | 30‑pin shrink DIP |
| Standby current consumption | 1.4 µA (typical at Vpp = 5.25 V) |
It operates from a supply voltage of 4.75 V to 5.25 V.
The shift register length can be set between 2 and 65 steps.
The device supports a maximum clock frequency of 33.3 MHz.
It is available in a 30‑pin shrink DIP package.