This document introduces the MCF5407 ColdFire processor, focusing on feature enhancements over the MCF5307
The MCF5407PB/D is a Version 4 ColdFire microprocessor core that combines a Harvard‑architecture memory system with 16‑Kbyte instruction cache, 8‑Kbyte data cache, two 2‑Kbyte on‑chip SRAMs, a MAC unit, divide unit, two UARTs (one synchronous), a four‑channel DMA controller, and two general‑purpose timers. It targets embedded control applications and delivers up to 316 Dhrystone MIPS at 220 MHz.
The device includes a System Integration Module, DRAM controller supporting up to 512 Mbytes, and a programmable PLL accepting 25‑54 MHz inputs for core frequencies of 100‑162 MHz. It is offered in a 208‑pin plastic QFP package and operates from –40 °C to 85 °C (162 MHz) or up to 70 °C (220 MHz).
| Core | Version 4 ColdFire processor core |
|---|---|
| Instruction cache | 16‑Kbyte |
| Data cache | 8‑Kbyte |
| On‑chip SRAM | Two 2‑Kbyte SRAMs |
| DMA channels | Four fully‑programmable channels |
| UARTs | Two UARTs, one supports synchronous operations |
| Timers | Two 16‑bit general‑purpose multimode timers |
| Dhrystone performance | 316 MIPS at 220 MHz, 233 MIPS at 162 MHz |
| Package | 208‑pin plastic QFP |
| Core clock range | 100‑162 MHz |
| PLL input range | 25‑54 MHz |
| Operating temperature | -40 °C to 85 °C (162 MHz) / up to 70 °C (220 MHz) |
The MCF5407 delivers 316 Dhrystone MIPS at 220 MHz and 233 Dhrystone MIPS at 162 MHz.
It includes four fully‑programmable DMA channels.
It uses a Harvard architecture with separate instruction and data buses.
The processor has two UARTs, and one of them supports synchronous communications.