The CMOS-6 family (CMOS‑6, CMOS‑6A, CMOS‑6V, CMOS‑6X) is a 1.0‑micron silicon‑gate, channelless gate‑array technology offering high‑density integration for ASIC applications. Devices feature internal gate delays of 270 ps and variable output‑drive currents up to 18 mA.
NEC supplies a range of ceramic PGA and flat‑pack packages, including a 184‑pin 0.65 mm QFP, and provides extensive design support through its OpenCAD® system, block libraries, and a network of ASIC Design Centers worldwide.
| Process technology | 1.0‑micron silicon‑gate CMOS |
|---|---|
| Variable output drive | 4.5, 9.0, 13.5, or 18.0 mA |
| Internal gate delay | 270 ps |
| Operating temperature range | -40 °C to +85 °C |
The internal gate delay is 270 ps.
Four output‑drive options are offered: 4.5 mA, 9.0 mA, 13.5 mA, and 18.0 mA.