The PB6100 (TTL‑2) series offers three high‑speed, low‑power bipolar gate arrays with 256, 598, and 918 internal cells. Devices are supplied in a wide range of DIP, flat and PGA packages, allowing designers to reduce component count and board size.
NEC supplies full CAD support, rapid design‑rule checking, automatic placement and routing, and a turn‑around time of 8‑10 weeks. Detailed electrical characteristics, absolute maximum ratings, and recommended operating conditions are listed for each package type.
| High speed | 2.5 ns/gate |
|---|---|
| Low power | 1.4 mW/gate |
| Turn‑around time | 8‑10 weeks |
| Power supply voltage (Vcc) | 5.0 V ±0.5 V |
| Operating temperature | 0 to +85 °C |
| Low‑level output current | 72 mA max |
| Cell count (wPB6101) | 256 |
| Cell count (wPB6102) | 598 |
| Cell count (wPB6103) | 918 |
NEC offers a quick turn‑around time of 8 to 10 weeks for the PB6100 gate arrays.