This document introduces the LTC3831, a high power, high efficiency DDR memory termination switching regulator controller. The device uses a synchronous switching architecture with N-channel MOSFETs, and the output voltage is equal to 1/2 of the external supply or reference voltage. The LTC3831 can sense output current and regulate it through the drain-source resistance of the upper N-channel MOSFET, thereby providing adjustable current limit without a current sense resistor. The device can operate with a supply voltage as low as 3V and with a maximum duty cycle of >91%. It includes a fixed frequency PWM oscillator for low output ripple operation.
The LTC3831 is a high‑power, high‑efficiency switching regulator controller designed for DDR memory termination. It generates an output voltage equal to one‑half of an external supply or reference voltage and uses a synchronous switching architecture with external N‑channel MOSFETs. The device includes an onboard PWM generator, ratiometric reference, and programmable features such as soft‑start, external clock synchronization, and adjustable frequency.
The document lists absolute maximum ratings, electrical characteristics, typical performance curves, pin functions, recommended layout, and related part numbers. It also provides application notes for DDR SDRAM termination, SSTL_2 and SSTL_3 interfaces, and guidance on using the controller in high‑power synchronous switching regulator designs.
| Supply Voltage Range | 3 V to 8 V |
|---|---|
| Maximum Duty Cycle | > 91 % |
| Shutdown Current | < 10 µA |
| Oscillator Frequency (free‑running) | ≈ 200 kHz (adjustable 100 kHz–500 kHz) |
| Package | 16‑lead narrow SSOP |
The LTC3831 operates with an input supply voltage as low as 3 V and up to 8 V.
The controller can achieve a maximum duty cycle greater than 91 %.
In shutdown mode the LTC3831’s quiescent current drops to less than 10 µA.
It is supplied in a 16‑lead narrow SSOP package.