The MAX97003 is a high-efficiency, low-noise audio subsystem that combines a mono speaker amplifier with a stereo headphone amplifier. The headphone and speaker amplifiers have independent volume and on/off controls. The four inputs can be configured as two differential or four single-ended inputs. To minimize output noise, both the headphone and speaker outputs utilize a downward expander/noise gate to attenuate noise when no desired input signal is present. The speaker output incorporates an adjustable dynamic range compressor (DRC) and distortion limiter to protect the speaker and maximize loudness. This allows high gain for low-level signals without compromising the quality of large signals. All controls are performed using the two-wire I2C interface. The IC operates in the extended -40°C to +85°C temperature range, and is available in the 2.0mm x 2.4mm, 20-bump WLP package (0.4mm pitch). Applications include cell phones and portable media players.
The MAX97003 audio subsystem combines a mono speaker amplifier with a stereo headphone amplifier. Both amplifiers have independent volume and on/off controls, and the four inputs can be configured as two differential or four single‑ended inputs. Output noise is reduced by a downward expander/noise gate, and the speaker output includes an adjustable dynamic‑range compressor and distortion limiter.
All functions are accessed via a two‑wire I²C interface. The device operates from –40 °C to +85 °C and is offered in a 2.0 mm × 2.4 mm, 20‑bump wafer‑level package (0.4 mm pitch). Detailed electrical characteristics, timing diagrams, and layout recommendations are provided for designers.
| Operating Temperature Range | –40 °C to +85 °C |
|---|---|
| Package | 2.0 mm × 2.4 mm, 20‑bump WLP (0.4 mm pitch) |
The SDA and SCL pull‑up voltage is 1.8 V.
The four inputs can be configured as two differential or four single‑ended inputs.
Yes, both the headphone and speaker outputs use a downward expander/noise gate to reduce output noise.
It is available in a 2.0 mm × 2.4 mm, 20‑bump wafer‑level package with 0.4 mm pitch.