TEXAS INSTRUMENTS TSD41AB1 handbook

This product is a IEEE 1394a-2000 fully compliant controller that supports 100/200/400 megabits per second of transmission speed.


TEXAS INSTRUMENTS TSD41AB1 handbook - cover page
Brand
Texas Instruments
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
68
File format
PDF
File size
1.6 MB
Published
04 May, 2012
Updated
30 September, 2023
MD5 checksum
16D4BF094428B5C720A42DD7916B800B

About this manual

The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one‑port node in an IEEE 1394 network. It includes circuitry for line monitoring, arbitration, packet reception and transmission, and supports optional isolation barriers. The device operates with a 24.576 MHz external crystal and generates a 49.152 MHz system clock for synchronization with the linked‑layer controller.

The datasheet includes pin‑out diagrams for PAP, GQE, ZQE and other package options, describes power‑down and suspend/resume behavior, and lists electrical specifications such as bias voltage, data rates, and external resistor values. A land‑pattern guide and important warranty notice are also provided.

What's inside

  • Description
  • Pin Diagrams
  • Package Options
  • Power and Bias
  • Operation Modes
  • Suspend/Resume
  • Power‑Down Function
  • LPS and C/LKON Signals
  • Land Pattern
  • Important Notice

Specifications

Supported data rates98.304, 196.608, 393.216 Mbits/s
System clock frequency49.152 MHz
External crystal requirement24.576 MHz
TPBIAS nominal voltage1.86 V
Power‑down energy reductionup to 210 %

Frequently asked questions

What data rates does the TSB41AB1 support?

It supports three data rates: 98.304 Mbits/s, 196.608 Mbits/s, and 393.216 Mbits/s.

What bias voltage is provided on the TPBIAS terminal?

The device provides a nominal 1.86‑V bias voltage at the TPBIAS terminal.

What external crystal frequency is required for the TSB41AB1?

A 24.576 MHz external crystal is required as the reference clock.

How does the TSB41AB1 achieve low power consumption?

The power‑down function disables the PLL and most internal circuits, reducing energy use by up to 210 %.

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