This datasheet provides a detailed description of the DS90C387/DS90CF388 dual pixel LVDS display interface (LDI).
The DS90C387/DS90CF388 transmitter‑receiver pair provides a dual‑pixel LVDS display interface (LDI) supporting resolutions from SVGA to QXGA. It converts 48‑bit (dual‑pixel 24‑bit color) CMOS/TTL data into eight LVDS streams and supports additional modes for single‑pixel operation and FPD‑Link compatibility.
Key features include up to 112 MHz dual‑pixel clock (672 Mbps per LVDS line, 5.38 Gbps total), pre‑emphasis and DC‑balance to reduce cable loading and ISI, and a cable‑deskew function that allows cables longer than 5 m. The device complies with the OpenLDI and ANSI/TIA/EIA‑644‑1995 LVDS standards and is 5 V tolerant on data and control inputs.
| Maximum dual‑pixel clock rate | 112 MHz |
|---|---|
| LVDS data line speed | 672 Mbps |
| Total data throughput | 5.38 Gbps |
| Cable deskew capability | ±1 LVDS data bit time (up to 80 MHz) |
| Supported panel resolutions | SVGA through QXGA |
| 5 V tolerance on inputs | Yes |
The device can deliver up to 5.38 Gbps of total throughput.
Cables longer than 5 m can be driven when pre‑emphasis and DC‑balance are enabled.
DS90C387 supports 32.5 to 112 MHz; DS90CF388 supports 40 to 112 MHz.
Yes, pre‑emphasis reduces cable loading effects and DC‑balance reduces ISI distortion.