This document provides an overview of the features and functions of the DS90C383B +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz.
The DS90C383B converts 28 bits of CMOS/TTL data into four LVDS data streams and provides a phase‑locked transmit clock on a fifth LVDS link. It supports spread‑spectrum clocking, low power dissipation (typical 130 mW at 65 MHz) and is compatible with VGA, SVGA, XGA and dual‑pixel SXGA displays.
The device is supplied in a 56‑lead TSSOP (MTD56) package and includes programmable edge‑strobe selection via the R_FB pin. Comprehensive electrical characteristics, pin descriptions, timing diagrams and mechanical dimensions are provided for system designers.
| Supply Voltage (Vcc) | -0.3 V to +4 V |
|---|---|
| Transmitter Supply Current at 65 MHz | 48 mA to 60 mA |
| Maximum Data Throughput | 1.8 Gbps (227 MB/s) |
| Power‑Down Current | < 60 µW (typ) |
The transmitter can handle up to 1.8 Gbps, which corresponds to a data throughput of 227 megabytes per second.
The recommended supply voltage (Vcc) range is from –0.3 V to +4 V.
It is offered in a 56‑lead TSSOP package (MTD56).