This document describes the features and characteristics of the M74HC138 high-speed CMOS 3-to-8 line decoder. The decoder is fabricated with silicon gate C2MOS technology and has features such as high speed, low power dissipation, and high noise immunity. It has 3 binary select inputs and 8 outputs, making it suitable for address decoders and memory systems.
The M74HC138 is a high‑speed, low‑power CMOS 3‑to‑8 line decoder with inverting outputs. It operates over a wide supply voltage range (2 V to 6 V) and offers balanced propagation delays, high noise immunity, and symmetrical output impedance. The device is pin‑compatible with the 74 series 138 family and includes three enable inputs for easy cascading in memory address decoding applications.
The datasheet details absolute maximum ratings, recommended operating conditions, DC and capacitive electrical characteristics, as well as mechanical dimensions for DIP‑16, SO‑16, and TSSOP‑16 packages. It also includes truth tables, pin descriptions, and typical propagation‑delay waveforms.
| Supply voltage range | 2 V to 6 V |
|---|---|
| Typical propagation delay (tpp) at 6 V | 13 ns |
| Maximum power dissipation | 500 mW at 65 °C |
| Input high‑level voltage (Vih) typical | 2.0 V |
The device operates from 2 V to 6 V.
Typical propagation delay is 13 ns when VCC is 6 V.
The part is offered in DIP‑16, SO‑16, and TSSOP‑16 packages.