This product is an 8-bit transparent D latch with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads.
The SN54AC573 and SN74AC573 are octal D‑type transparent latches with three‑state outputs. When the latch‑enable (LE) input is high, the Q outputs follow the D inputs; when LE is low, the outputs retain the last state. An output‑enable (OE) pin allows the outputs to be placed in a high‑impedance state for bus‑sharing applications.
The document includes ordering information for multiple package options (PDIP, SOIC, SSOP, TSSOP, etc.), mechanical drawings, absolute‑maximum ratings, recommended operating conditions, timing diagrams, and a package‑option addendum. Additional product details and the latest availability can be found on TI’s website.
| Maximum propagation delay (tpg) | 9 ns @ 5 V |
|---|
The maximum tpg is 9 ns at a 5 V supply.
OE should be tied to Vcc through a pull‑up resistor.