Intersil ISL9011 Dual LDO Datasheet

ISL9011 is a high performance dual LDO from Infineon. It has a low standby current and high-PSRR and is stable with output capacitance of 1µF to 10µF with ESR of up to 200mΩ. A reference bypass pin allows an external capacitor for adjusting a noise filter for low noise and high PSRR applications. The quiescent current is typically only 45µA with both LDO’s enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1µA.


Intersil ISL9011 Dual LDO Datasheet - cover page
Brand
Intersil
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
11
File format
PDF
File size
205 KB
Published
28 March, 2012
Updated
30 September, 2023
Model
ISL9011
MD5 checksum
28329F8BD8DE54C30DBA280136FDD7FE

About this manual

The ISL9011 integrates two low‑noise LDO regulators in a compact 10‑lead DFN package. Each channel can be enabled independently, provides up to 150 mA (VO1) or 300 mA (VO2), and features a low dropout voltage of about 120 mV at 150 mA.

Typical applications include portable instruments, smartphones, MP3 players, and medical handheld devices where low standby current (≈45 µA) and high PSRR (70 dB @ 1 kHz) are critical. The device includes soft‑start, over‑current, and over‑temperature protection.

What's inside

  • Features
  • Ordering Information
  • Absolute Maximum Ratings
  • Recommended Operating Conditions
  • Electrical Specifications
  • Device Start‑up Characteristics
  • Pin Description
  • Typical Application
  • Typical Performance Curves
  • Package Dimensions

Specifications

VO1 Output Current150 mA
VO2 Output Current300 mA
Quiescent Current (both LDOs active)45 µA
Dropout Voltage (VO1 @ 150 mA)≈120 mV
Power Supply Rejection Ratio70 dB @ 1 kHz
Input Voltage Range2.3 V to 6.5 V
Operating Temperature Range-40 °C to +85 °C
Package10‑lead DFN 3 mm × 3 mm

Frequently asked questions

What is the quiescent current when both LDOs are active?

The device draws only about 45 µA of quiescent current with both LDOs enabled.

Which output powers up first when both enable pins are activated simultaneously?

VO1 has priority and is always powered up before VO2 when EN1 and EN2 go high at the same time.

What happens if EN2 is enabled before EN1?

If EN2 goes high first, VO1 turns on first and the device delays VO2 until VO1 reaches its target voltage.

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