Intersil X9241A Quad Digital Controlled Potentiometer Datasheet

The X9241A is a chip that integrates four digitally controlled potentiometers, with features such as non-volatile, low power, 2-wire, and 64 taps. It can be used as a three-terminal potentiometer or a two-terminal variable resistor.


Intersil X9241A Quad Digital Controlled Potentiometer Datasheet - cover page
Brand
Intersil
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
16
File format
PDF
File size
260 KB
Published
27 March, 2012
Updated
29 September, 2023
Model
X9241A
MD5 checksum
648471713526A0DA7ED1719C2124A5B3

About this manual

The X9241A is a highly integrated CMOS microcircuit that combines four digitally controlled potentiometers, each with 64 taps, into a single package. It offers a 2‑wire serial interface (SCL/SDA) for low‑power communication and includes volatile wiper counters and four non‑volatile data registers per pot.

Key features include 64‑tap resolution per potentiometer, 16 bytes of non‑volatile memory, 100‑year register data retention, and an endurance of 100 000 data changes per bit per register. The device is available in PDIP, SOIC, and TSSOP packages with temperature ranges from –40 °C to +85 °C.

What's inside

  • Features
  • Ordering Information
  • Pin Descriptions
  • Principles of Operation
  • Serial Interface
  • Device Addressing
  • Instruction Set
  • Detailed Operation
  • Wiper Counter Register
  • Data Registers

Specifications

Resolution64 taps per potentiometer
Endurance100,000 data changes per bit per register
Register data retention100 years
Non‑volatile memory16 bytes
Supply voltage+5 V, –3.0 V
Temperature range (SOIC/TSSOP)–40 °C to +85 °C

Frequently asked questions

What type of interface does the X9241A use?

It uses a 2‑wire serial interface (SCL and SDA) with a bidirectional bus protocol.

How many taps does each potentiometer have?

Each potentiometer provides 64 taps.

What is the endurance of the data registers?

The data registers can endure 100,000 data changes per bit per register.

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