Atmel AT24C32C/AT24C64C EEPROM Datasheet

The AT24C32C/64C is a serial electrically erasable and programmable read-only memory (EEPROM) with low power and low voltage operation. It provides 32,768/65,536 bits of storage space and is accessed via a 2-wire serial interface. The device is suitable for many industrial and commercial applications.


Atmel AT24C32C/AT24C64C EEPROM Datasheet - cover page
Brand
Atmel
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
27
File format
PDF
File size
860 KB
Published
27 March, 2012
Updated
28 September, 2023
MD5 checksum
587832A9E5957858D27D757DC3A47C11

About this manual

The AT24C32C/AT24C64C series provides 32‑kbit and 64‑kbit serial EEPROM memory organized as 4096 × 8 and 8192 × 8 bits respectively. The devices operate over a 1.8 V to 5.5 V supply range and support low‑power, low‑voltage applications with up to eight devices cascaded on a common 2‑wire I²C bus.

The datasheet includes electrical characteristics, pin descriptions, timing diagrams, and operating procedures such as write protection, standby mode, and software reset. Package options include PDIP, SOIC, TSSOP, ULA, MLP, and BGA variants.

What's inside

  • Features
  • Pin Description
  • Memory Organization
  • Absolute Maximum Ratings
  • DC Characteristics
  • AC Characteristics
  • Device Operation
  • Bus Timing
  • Write Cycle Timing
  • Revision History

Specifications

Supply Voltage (VEE)1.8 V to 5.5 V
Operating Temperature-55 °C to +125 °C
Endurance1 Million write cycles
Data Retention100 years
Page Write Mode32‑byte page write (partial page writes allowed)
Maximum Clock Frequency400 kHz (1.8 V) to 1 MHz (5 V)

Frequently asked questions

How many AT24C32C/AT24C64C devices can be addressed on a single 2‑wire bus?

Up to eight devices can be cascaded on the same bus.

What does the Write Protect (WP) pin do?

When WP is high, all write operations are inhibited; when WP is low, normal write operations are allowed.

When does the device enter standby mode?

The EEPROM enters low‑power standby mode after power‑up and after a stop condition is received.

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