This document describes the features and characteristics of the ARM926EJ-S ARM Thumb processor, including DSP instruction extensions, ARM Jazelle technology, 16Kbyte data cache, 16Kbyte instruction cache, write buffer, 210 MIPS clock speed, memory management unit, EmbeddedICE debug communication channel support, mid-level implementation Embedded Trace Macrocell, and other embedded memories, external bus interface, LCD controller, USB, and bus matrix.
The AT91SAM9261 is a complete system‑on‑chip built around an ARM926EJ‑S Thumb processor with DSP extensions and Jazelle Java acceleration, delivering up to 210 MIPS at 190 MHz. It integrates 32 KB of internal ROM, 160 KB of SRAM, a 217‑ball LEBGA RoHS‑compliant package, USB 2.0 host and device ports, and an LCD controller capable of 16‑M‑color TFT displays.
The datasheet details the chip’s architecture, including the bus matrix, power management controller, interrupt controller, and peripheral interfaces such as SDRAM, NAND/CompactFlash, USARTs, SPI, I2C, and multimedia card. It also lists voltage supply requirements, pin‑out tables, signal descriptions, and a revision history of the document.
| Processor Core | ARM926EJ‑S Thumb |
|---|---|
| Maximum Performance | 210 MIPS at 190 MHz |
| Internal ROM | 32 KB |
| Internal SRAM | 160 KB |
| Package | 217‑ball LEBGA, RoHS‑compliant |
| USB Host | USB 2.0 Full Speed (12 Mbps) Double Port |
| Core Voltage Supply (VDDCORE) | 1.08 V – 1.32 V |
| Peripheral I/O Voltage (VDDIOP) | 2.7 V – 3.6 V |
It uses an ARM926EJ‑S Thumb processor with DSP extensions and Jazelle Java acceleration.
The chip includes nineteen Peripheral DMA (PDC) channels.
It supports up to 16 M colors in TFT mode with a maximum resolution of 2048 × 2048 pixels.